NXP Semiconductors /MK64F12 /SystemControl /FPDSCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FPDSCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)RMode 0 (0)FZ 0 (0)DN 0 (0)AHP

AHP=0, FZ=0, DN=0, RMode=00

Description

Floating-point Default Status Control Register

Fields

RMode

Default value for FPSCR.RMode (Rounding Mode control field).

0 (00): Round to Nearest (RN) mode

1 (01): Round towards Plus Infinity (RP) mode.

2 (10): Round towards Minus Infinity (RM) mode.

3 (11): Round towards Zero (RZ) mode.

FZ

Default value for FPSCR.FZ (Flush-to-zero mode control bit).

0 (0): Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.

1 (1): Flush-to-zero mode enabled.

DN

Default value for FPSCR.DN (Default NaN mode control bit).

0 (0): NaN operands propagate through to the output of a floating-point operation.

1 (1): Any operation involving one or more NaNs returns the Default NaN.

AHP

Default value for FPSCR.AHP (Alternative half-precision control bit).

0 (0): IEEE half-precision format selected.

1 (1): Alternative half-precision format selected.

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